Methods for improving coupling ratio of the memory cell of a non-volatile semiconductor memory device have been proposed (e.g., Japanese Patent Laid-Open No. 2003-23115).
As a method for improving the coupling ratio of a memory cell known by the present applicant, not a heretofore known technique, there is a method for enlarging the surface area of a floating gate electrode facing a control gate electrode by etching an isolation oxide film serving as element isolation structure by a predetermined thickness to expose the sides of a control electrode. This method will be described below.
FIGS. 17A to 24 are sectional process views for illustrating a method for manufacturing a non-volatile semiconductor memory device according to Background Art.
First, as FIG. 17A shows, a thermal oxide film 2 is formed on a silicon substrate 1, and a silicon nitride film 3 is formed on the thermal oxide film 2. Further, a resist pattern 4, whose portion corresponding to an element isolation region is opened, is formed on the silicon nitride film 3 using photoengraving.
Next, the silicon nitride film 3 and the thermal oxide film 2 are sequentially subjected to dry etching using the resist pattern 4 as a mask. Thereafter, the resist pattern 4 is removed. Then, the silicon substrate 1 is etched using the patterned silicon nitride film 3 as a mask. Thereby, as FIG. 17B shows, trenches 5 are formed in the silicon substrate 1.
Next, a thermal oxide film (not shown) is formed on the internal walls of the trenches 5. Thereafter, as FIG. 18A shows, a silicon oxide film 6 to be an isolation oxide film is formed on the entire surface of the substrate 1. Next, as FIG. 18B shows, the silicon oxide film 6 is planarized by a CMP (chemical mechanical polishing) method using the silicon nitride film 3 as a stopper film.
Next, the silicon nitride film 3 is removed using hot phosphoric acid to form a structure shown in FIG. 19A. Further, the thermal oxide film 2 is removed using hydrofluoric acid to form a structure shown in FIG. 19B. FIG. 25 is a top view showing active regions in a memory cell array according to Background Art. As FIG. 25 shows, a plurality of rectangular active regions A are formed in line in the shorter side direction. The isolation silicon oxide film 6 serving as element isolation structures is formed so as to isolate the active regions A.
Next, as FIG. 20A shows, a thermal oxide film 7 to be a tunnel oxide film is formed on the surface of the substrate 1. A polysilicon film 8 to be a floating gate electrode of the memory cell is formed on the entire surface of the substrate 1.
Next, as FIG. 20B shows, the polysilicon film 8 is planarized by a CMP method using the isolation oxide film 6 as a stopper film. Thereby, the surface of the silicon oxide film 6 has the same height as the surface of the polysilicon film 8. Here, the polysilicon film 8 is self-aligned to the isolation oxide film 6.
Next, as FIG. 21A shows, the isolation silicon oxide film 6 is selectively etched by a predetermined thickness using hydrofluoric acid. Thereby, the upper portions of the sides of the polysilicon film 8 are exposed. Therefore, the surface area of the floating gate electrode 8 facing the control gate electrode can be enlarged, and the coupling ratio of the memory cell can be improved.
Thereafter, as FIG. 21B shows, an ONO film 10 is formed on the entire surface of the substrate 1. The ONO film 10 is made by stacking a silicon oxide film, a silicon nitride film and a silicon oxide film.
Next, as FIG. 22A shows, a resist pattern 11 covering the memory cell region is formed using photoengraving.
Then, as FIG. 22B shows, the ONO film 10 and the polysilicon film 8 of the peripheral circuitry are sequentially subjected to dry etching using the resist pattern 11 as a mask. Further, the thermal oxide film 7 of the peripheral circuitry is removed using hydrofluoric acid. Thereafter, the resist pattern 11 is removed to form a structure shown in FIG. 23A. Here, as FIG. 23A shows, in the peripheral circuitry, the surface of the isolation oxide film 6 falls below the surface of the substrate 1 to produce a step B. The step B causes problems described below.
Next, as FIG. 23B shows, in the peripheral circuitry, a thermal oxide film 12 to be a gate oxide film is formed on the surface of the substrate 1. Then, a polysilicon film 13 and a WSi film 14 as conductive films to be the control gate electrode of the memory cell and to be the gate electrode of the peripheral circuitry are sequentially formed. A silicon nitride film 15 is formed on the WSi film 14. Further, a resist pattern 16 covering the control gate electrode portion and the gate electrode portion is formed on the silicon nitride film 15 using photoengraving.
Next, as FIG. 24 shows, the silicon nitride film 15 is subjected to dry etching using the resist pattern 16 as a mask. Thereafter, the resist pattern 16 is removed. Then, the WSi film 14 and the polysilicon film 13 are sequentially subjected to dry etching using the patterned silicon nitride film 15 as a mask. At this time, since the step B is present on the element isolation oxide film 6 of the peripheral circuitry as described above, there is high possibility that etching residues (polysilicon residues) 13a are formed in the portion of the step B.
In the above-described manufacturing method, when the isolation oxide film 6 was etched in order to improve the coupling ratio of the memory cell, the isolation oxide film 6 in the peripheral circuitry was also etched. Therefore, when the ONO film 10 and the thermal oxide film 7 in the peripheral circuitry were removed, there was a problem that the isolation oxide film 6 was further etched, the isolation oxide film 6 fell much below the surface of the substrate 1, and the step B was formed. Therefore, when the gate electrode was patterned, there was a problem that etching residues 13a were formed in the step B. There was a problem that the circuit elements that should be insulated under normal circumstances were conducted through the residues 13a, and thereby causing a defective circuit.